Modem computer systems often include many voltage supplies. These are generated using DC/DC converters. A buck converter, a type of converter, can be used to step-down the voltage from a main DC supply. Depending on the voltage conversion ratio, buck converters, also referred to as Voltage Regulator Modules (VRM), have a power efficiency in the range of 70%-90%. To improve both power efficiency and voltage regulation, the recent trend is to move towards fully integrated voltage regulator (FIVR) modules to supply both the core and I/O circuits for System on Chip (SOC) applications. One implementation of a FIVR is to integrate the buck converter with SOC as a two chip solution on a package with passives such as inductors and capacitors either surface mounted or embedded in the package. Such two chip solutions can utilize a buck converter as the first chip and a Low Dropout regulator (LDO) as the second chip.
To ensure fine grained power management with fast transient response, LDOs are integrated in the SOC in close proximity to the load. Several LDOs integrated in the SOC are used to provide voltage regulation for both the core (i.e., the main bulk of the digital logic circuit with higher power consumption but usually operating at a lower frequency) and the I/O circuits. Voltage from the buck converter is supplied to the LDOs using voltage and ground planes in the package and/or printed circuit board (PCB).
Often times, voltage islands are used to separate the core and I/O power distribution to minimize noise coupling between the two. One limitation of the LDOs is the power supply rejection (PSR) peaking that occurs when its regulating feedback loop gain reaches 1 or 0 dB. Around this frequency, the PSR of the LDO degrades, resulting in power supply noise passing through the LDO from its input to its output, which connects to the power supply nodes of I/O drivers or other types of loads through the power delivery network (PDN), without impediment. Hence, it is important to keep power supply noise low by controlling the impedance at the input of the LDO in this frequency range. Unfortunately, for typical LDOs, the PSR peaking occurs in the 50 MHz-100 MHz frequency range, in where the chip-package or board anti-resonances also occur. An anti-resonance means a high impedance peak. A combination of ineffective noise rejection capability of the LDO due to PSR peaking and large package/board impedances can reduce the bandwidth of the LDO regulator leading to excessive power supply noise coupling from the input to the output of the LDO. A common way to improve PSR is by increasing the voltage dropout from the LDO input to the output so less noise voltage gets through to the output. However, this method also implies more power is dissipated in the LDO by the high dropout voltage causing decreased LDO efficiency. This is especially the case for LDO regulators used for I/O drivers.
Therefore, there is a need to enhance the bandwidth of the LDO to provide clean power to I/O drivers, while maintaining or improving the overall energy efficiency of the power delivery network that includes LDOs.